This invention relates generally to delay lock loop (DLL) circuits, and more particularly to a no-resonance bang-bang phase detector in a DLL for low jitter applications.
DLLs have been widely used for reducing clock skew. FIG. 1 is a simplified block diagram of a conventional DLL circuit 100. The circuit l00 includes a reference clock signal line 101, a clock variable delay unit 102, a clock feedback signal line 103, and a phase detector 106 having a lead output and a lag output. Most conventional DLL circuits use either a bang-bang phase detector (BBPD) or a linear phase detector (LPD) as the phase detector 106. The circuit 100 further includes a filter 108, a lock circuit 110, and reference clock output 109.
When the DLL circuit 100 is in lock mode, oscillation will occur at the output of the phase detector 106. In the case where a BBPD is used, resonance will develop which results in a nonlinear behavior for the DLL circuit 100. Unfortunately, the jitter performance of most DLLs is limited by the nonlinear behavior BBPDs because there is oscillation at lock mode. Alternatively, the LPD is very difficult to implement digitally.
What is needed is a BBPD without a resonance mode, having an operation more like a LPD. Further, what is needed is a phase detector circuit having low jitter.
This invention provides a phase detector circuit that eliminates oscillation in order to achieve low jitter performance. Embodied as a bang-bang phase detector (BBPD), the present invention operates much like a linear phase detector (LPD). The invention, in combination with a nonlinear digital filter, also provides a low-jitter performance for a delay lock loop (DLL) circuit.
According to one embodiment of the invention, a BBPD circuit includes a data signal line, a clock signal line, and a delay cell having an input coupled to the data input. The BBPD circuit further includes a first double flip-flop having a data input coupled to the data signal line and a clock input coupled to the clock signal line, and a second double flip-flop having a data input coupled to an output of the delay cell and a second input coupled to the clock signal line. The circuit further includes a NOR circuit having a first input coupled to an output of the first double flip-flop and a second input coupled to an output of the second double flip-flop. The circuit provides a lag output signal line coupled to an output of the NOR circuit, and a lead output signal line coupled to the output of the fourth flip-flop.
According to another embodiment of the invention, a delay lock loop (DLL) system or circuit includes a variable delay unit for receiving a reference clock signal, a clock buffer for receiving a clock feedback signal, and a phase detector. The phase detector includes a delay cell having an input for receiving an output of the variable delay unit, and a first sequential logic circuit having an input for receiving the output of the variable delay unit and a clock input for receiving the clock feedback signal. The phase detector further includes a second sequential logic circuit having an input for receiving an output of the delay cell, an input for receiving the clock feedback signal, and an output for outputting a lead signal. The phase detector further includes a NOR circuit having a first input for receiving an output of the first sequential logic circuit, a second input for receiving an output of the second sequential logic circuit, and an output for outputting a lag signal. The DLL further includes a nonlinear digital filter and control circuit for receiving the lead signal and lag signal, and for controlling the variable delay unit, and a lock circuit for receiving an output from the filter/control circuit and outputting an DLL output.
In accordance with the invention, the BBPD circuit operates much like a phase detector, and combined with a nonlinear digital filter, achieves low jitter. The BBPD operates according to a no-resonance mode to eliminate oscillation within the DLL.